1. Field of the Invention
The present invention relates to memory devices and systems including error correction code (ECC) logic.
2. Description of Related Art
Memory technologies used for integrated circuit memories are being developed at smaller and smaller technology nodes, and are being deployed on larger and larger memory arrays on a single integrated circuit. As the technology for memory cells advances, the margins for sensing the data can become tighter. Also, the ability of the memory cells to hold data values in the presence of disturbance of the memory cell state caused by high speed and high volume accesses to the memory cells and to neighboring memory cells can be limited by the tighter margins.
To address issues like those that arise from tighter sensing margins and memory cell disturbance, as these technologies scale in size and density, use of error correcting codes (ECCs) and supporting logic embedded with integrated circuit memory has become more widespread.
In some systems, the threshold voltage, or other sensing conditions, of memory cells can drift over time, or with cycling of the data. Technology has been proposed to account for this drift in the reading and programming operations by moving the read bias conditions to match the drift. See for example, U.S. Pat. No. 6,992,932 by Cohen, and Polansky et al., “A 4b/cell NROM 1 Gb Data-Storage Memory,” ISSCC 2006, Session 7/Non-Volatile Memory/7.1, January 2006.
Notwithstanding the range of error correction technologies, error rates can still limit the usefulness of existing memory technologies, and slow the adoption of new memory technologies. Thus, it is desirable to improve error correction technologies as applied to memory devices.